1. Field of the Invention
The present invention relates to a method of fabricating a silicon-on-insulator device. The invented method is particularly relevant to fully depleted silicon-on-insulator devices.
2. Description of the Related Art
Complementary metal-oxide-semiconductor (CMOS) integrated circuits formed on conventional bulk silicon substrates are unable to provide the combination of high performance and low power consumption needed in advanced personal and mobile communication devices, because as their clock rates are increased to boost their performance, and as their internal dimensions are scaled down to permit higher levels of integration, they dissipate increasing amounts of power. Fully depleted silicon-on-insulator CMOS devices offer a promising solution to this problem.
A silicon-on-insulator (SOI) substrate can be created by implanting oxygen ions into a silicon substrate and annealing the substrate to form a buried oxide layer; transistors and other circuit elements are then formed in the silicon layer (the SOI layer) above the buried oxide. Since the transistors are completely isolated from one another by the buried oxide layer and by overlying field oxide layers, they can be laid out at high density without risk of latch-up. High-speed, low-power operation is possible because the parasitic capacitance of the sources and drains of the transistors is reduced. This is particularly true in a fully depleted (FD) SOI device, in which the SOI layer is thin enough to be inverted or depleted throughout its vertical extent. A fully depleted SOI device has a nearly ideal subthreshold coefficient, enabling the transistor threshold voltage to be reduced by about 0.1 volt, for a given level of subthreshold leakage current, as compared with a transistor formed in a bulk silicon substrate. This feature is especially valuable in devices operating at low power-supply voltages.
Although fully depleted SOI devices have many advantages, they also have an unwanted feature: a subthreshold hump in the drain current vs. gate voltage operating characteristic, due to the formation of a parasitic channel at the edges of the active regions of transistors. In effect, each transistor is flanked by two parasitic transistors with lower threshold voltages. These parasitic transistors leak unwanted current in the off state. As a result, conventional fully depleted SOI devices draw more current than expected during standby periods, when the device is powered but is not operating.
This problem is not confined to fully depleted SOI devices; it can also appear in SOI devices of the partially depleted type.